1. Field of the Invention
The present invention relates to a technique of verifying a semiconductor integrated circuit. In particular, the present invention relates to a technique of verifying placement of IO cells in an IO region of a semiconductor integrated circuit.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-127577, filed on May 14, 2007, the disclosure of which is incorporated herein in its entirely by reference.
2. Description of Related Art
FIG. 1 is a flowchart showing a typical method of designing a semiconductor integrated circuit. First, a cell library is prepared (Step S1). The cell library consists of cell data of various kinds of cells. The various kinds of cells include a macro cell, a primitive cell, an IO cell and the like.
Next, floor planning is performed based on a user netlist (Step S2). In the floor planning, locations of macro cells and paths of power lines are roughly determined. Next, IO cells are placed in an IO region based on the result of the floor planning (Step S3). The IO region (peripheral region) is peripheral to a layout region. Subsequently, power routing is performed in which a layout of power lines and ground lines are determined (Step S4). Next, placement of primitive cells and routing of signal interconnections are performed (Step S5). As a result, a layout data indicating a layout of a design circuit is completed (Step S6).
After that, verification of the layout data is performed (Step S7). The layout verification includes DRC (Design Rule Check), LVS (Layout Versus Schematic) and the like. In the DRC, it is verified whether or not the layout meets the design rule. In the LVS, it is verified whether or not the layout accords with the user netlist, namely, whether or not elements and connections between the elements in a logic design stage are correctly reproduced in the layout.
A representative one of the above-mentioned IO cells is an input-output buffer. In general, only information of the input and the output is given to the cell data of the input-output buffer. Therefore, it has been difficult to perform the LVS verification in consideration of a power line and a ground line within the input-output buffer. A technique for solving the problem is disclosed in Japanese Laid-Open Patent Application JP-2006-155524.
According to a method of verifying a semiconductor integrated circuit described in Japanese Laid-Open Patent Application JP-2006-155524, “physical information” is given to the cell data of the input-output buffer. The physical information indicates locations of a power line and a ground line within the input-output buffer. In the LVS verification, placement verification of input-output buffers is performed based on the physical information. Consequently, it becomes possible to verify a connection of the power line between adjacent input-output buffers.
The inventor of the present application has recognized the following points. There exist an IO cell having a certain function and another cell for driving the IO cell in the IO region of a semiconductor integrated circuit. The former is referred to as a “controlled cell” and the latter is referred to as a “controlling cell” hereinafter. The controlling cell outputs a control signal for controlling an operation of the controlled cell, and the controlled cell is controlled by the control signal output by the controlling cell. That is to say, the controlled cell depends on the controlling cell. In order that the controlled cell operates normally, both of the controlled cell and the controlling cell need to be placed in a region through which the control signal is transmitted. If the controlling cell is not placed in the region, the controlled cell can not operate normally. Such a placement error should be detected during the layout design/verification stage.
However, the user netlist does not include information on the dependence relationship between the controlling cell and the controlled cell. Therefore, it is not possible in the typical LVS verification to detect an error that the controlling cell required by the controlled cell does not exist. If such a placement error is overlooked, a product does not operate normally.